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rev. b a ADF4252 dual fractional-n/integer-n frequency synthesizer one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. features 3.0 ghz fractional-n/1.2 ghz integer-n 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage to 5 v programmable dual modulus prescaler rf: 4/5, 8/9 if: 8/9, 16/17, 32/33, 64/65 programmable charge pump currents 3-wire serial interface digital lock detect power-down mode programmable modulus on fractional-n synthesizer trade-off noise versus spurious performance applications base stations for mobile radio (gsm, pcs, dcs, cdma, wcdma) wireless handsets (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment catv equipment functional block diagram ADF4252 2 doubler output mux 4-bit r counter phase frequency detector lock detect charge pump reference ref in ref out v dd 1 v dd 2 v dd 3 dv dd v p 1 v p 2 r set 24-bit data register clk data le rf in a rf in b cp rf cp if 2 doubler 15-bit r counter charge pump phase frequency detector muxout a gnd 1 a gnd 2 d gnd cp gnd 1 cp gnd 2 if in b if in a fractional n rf divider integer n if divider general description the ADF4252 is a dual fractional-n/integer-n frequency synthesizer that can be used to implement local oscillators (lo) in the upconversion and downconversion sections of wireless receivers and transmitters. both the rf and if syn- thesizers consist of a low noise digital pfd (phase frequency de tec tor), a precision charge pump, and a programmable refer- ence divider. the rf synthesizer has a - -based fractional interpolator that allows progr ammable fractional-n division. the if synthesizer has programmable integer-n counters. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an ex ternal loop filter and vco (volt- age controlled oscillator). control of all the on-chip registers is via a simple 3-wire inter- face. the devices operate with a power supply ranging from 2.7 v to 3.3 v and can be powered down when not in use.
rev. b ? ADF4252?pecifications 1 (v dd 1 = v dd 2 = v dd 3 = dv dd = 3 v 10%, dv dd < v p 1, v p 2 < 5.5 v, gnd = 0 v, r set = 2.7 k , dbm referred to 50 , t a = t min to t max , unless otherwise noted.) parameter b version unit test conditions/comments rf characteristics rf input frequency (rf in a, rf in b) 2 0.25/3.0 ghz min/max rf input sensitivity ?0/0 dbm min/max rf input frequency (rf in a, rf in b) 2 0.1/3.0 ghz min/max input level = ?/0 dbm min/max rf phase detector frequency 30 mhz max guaranteed by design allowable prescaler output frequency 375 mhz max if characteristics if input frequency (if in a, if in b) 2 50/1200 mhz min/max if input sensitivity ?0/0 dbm min/max if phase detector frequency 55 mhz max guaranteed by design allowable prescaler output frequency 150 mhz max reference characteristics ref in input frequency 250 mhz max for f < 10 mhz, use dc-coupled square wave (0 to v dd ). ref in input sensitivity 0.5/v dd 1v p-p min/max ac-coupled. when dc-coupled, use 0 to v dd max (cmos compatible). ref in input current 100 a max ref in input capacitance 10 pf max charge pump rf i cp sink/source high value 4.375 ma typ see table v low value 625 a typ if i cp sink/source high value 5 ma typ see table ix low value 625 a typ i cp three-state leakage current 1 na typ rf sink and source current matching 2 % typ 0.5 v < v cp < v p ?0.5 r set range 1.5/1.6 k typ see table v if sink and source current matching 2 % typ i cp vs. v cp 2% typ 0.5 v < v cp < v p ?0.5 i cp vs. temperature 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 1.35 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in input capacitance 10 pf max logic outputs v oh , output high voltage v dd ?0.4 v min i oh = 0.2 ma v ol , output low voltage 0.4 v max i ol = 0.2 ma power supplies v dd 1 , v dd 2, v dd 3 2.7/3.3 v min/v max dv dd v dd 1 v p 1, v p 2v dd 1/5.5 v min/v max i dd 3 rf + if 13 ma typ 16 ma max rf only 10 ma typ 13 ma max if only 4 ma typ 5.5 ma max power-down mode 1 a typ rf noise and spurious characteristics noise floor ?41 dbc/hz typ @ 20 mhz pfd frequency in-band phase noise performance 4 @ vco output lowest spur mode ?0 dbc/hz typ rf out = 1.8 ghz, pfd = 20 mhz low noise and spur mode ?5 dbc/hz typ rf out = 1.8 ghz, pfd = 20 mhz lowest noise mode ?03 dbc/hz typ rf out = 1.8 ghz, pfd = 20 mhz spurious signals see typical performance characteristics notes 1 operating temperature range (b version): ?0 c to +85 c. 2 use a square wave for frequencies less than f min . 3 rf = 1 ghz, rf pfd = 10 mhz, mod = 4095, if = 500 mhz, if pfd = 200 khz, ref = 10 mhz, v dd = 3 v, v p 1 = 5 v, and v p 2 = 3 v. 4 the in-band phase noise is measured with the eval-ADF4252eb2 evaluation board and the hp5500e phase noise test system. the spec trum analyzer provides the ref in for the synthesizer (f refout = 10 mhz @ 0 dbm). f out = 1.74 ghz, f ref = 20 mhz, n = 87, mod = 100, channel spacing = 200 khz, v dd = 3.3 v, and v p = 5 v. specifications subject to change without notice.
rev. b ADF4252 ? timing characteristics * limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width * guaranteed by design, but not production tested. (v dd 1 = v dd 2 = v dd 3 = dv dd = 3 v 10%, dv dd < v p 1, v p 2 < 5.5 v, gnd = 0 v, unless otherwise noted.) clock data le le t 4 t 2 t 3 t 5 t 7 t 6 db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) db23 (msb) t 1 figure 1. timing diagram
rev. b ? ADF4252 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADF4252 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package mode range option * ADF4252bcp C 40 o c to +85 o c cp-24 ADF4252bcp-reel C 40 o c to +85 o c cp-24 ADF4252bcp-reel7 C 40 o c to +85 o c cp-24 eval C ADF4252eb1 eval C ADF4252eb2 * cp = chip scale package pin configuration pin 1 indicator top view (not to scale) 18 cp gnd 2 17 dv dd 16 if in a 15 if in b cp rf 1 cp gnd 1 2 rf in a 3 24 v p 1 14 a gnd 2 13 r set ref in 7 ref out 8 d gnd 9 clk 10 data 11 le 12 rf in b 4 a gnd 1 5 muxout 6 23 v dd 1 22 v dd 3 21 v dd 2 20 v p 2 19 cp if ADF4252 absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd 1, v dd 2, v dd 3, dv dd to gnd 3 . . . . . . . . C 0.3 v to +4 v ref in , rf in a, rf in b to gnd . . . . . . C 0.3 v to v dd + 0.3 v v p 1, v p 2 to gnd . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +5.8 v v p 1, v p 2 to v dd 1 . . . . . . . . . . . . . . . . . . . . . C 3.3 v to +3.5 v digital i/o voltage to gnd . . . . . . . . C 0.3 v to v dd + 0.3 v analog i/o voltage to gnd . . . . . . . . C 0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C 65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c csp ja thermal impedance . . . . . . . . . . . . . . . . . . . 122 c/w soldering reflow temperature vapor phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240 c ir reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performance rf integrated circuit with an esd rating of <2 k ? , and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = cp gnd 1, a gnd 1, d gnd , a gnd 2, and cp gnd 2.
rev. b ADF4252 ? pin function descriptions mnemonic function cp rf rf charge pump output. this is normally connected to a loop filter that drives the input to an external vco. cp gnd 1 rf charge pump ground. rf in a input to the rf prescaler. this small signal input is normally taken from the vco. rf in bc omplementary input to the rf prescaler. a gnd 1a nalog ground for the rf synthesizer. muxout this multiplexer output allows either the rf or if lock detect, the scaled rf or if, or the scaled reference fre- quency to be accessed externally. ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k ? . this input can be driven from a ttl or cmos crystal oscillator. ref out reference output. d gnd digital ground for the fractional interpolator. clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the shift register on the clk rising edge. this input is a high impedance cmos input. data serial data input. the serial data is loaded msb first with the three lsbs being the control bits. this input is a high impedance cmos input. le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the seven latches, the latch being selected using the control bits. r set connecting a resistor between this pin and ground sets the minimum charge pump output current. the relationship between i cp and r set is i r cp set min = 1 6875 . therefore, with r set = 2.7 k ? , i cpmin = 0.625 ma. a gnd 2g round for the if synthesizer. if in bc omplementary input to the if prescaler. if in a input to the if prescaler. this small signal input is normally taken from the if vco. dv dd positive power supply for the fractional interpolator section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. dv dd must have the same voltage as v dd 1, v dd 2, and v dd 3. cp gnd 2i f charge pump ground. cp if if charge pump output. this is normally connected to a loop filter that drives the input to an external vco. v p 2i f charge pump power supply. decoupling capacitors to the ground plane should be placed as close as possible to this pin. this voltage should be greater than or equal to v dd 2. v dd 2p ositive power supply for the if section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 2 has a value 3 v 10%. v dd 2 must have the same voltage as v dd 1, v dd 3, and dv dd . v dd 3 positive power supply for the rf digital section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 3 has a value 3 v 10%. v dd 3 must have the same voltage as v dd 1, v dd 2, and dv dd . v dd 1 positive power supply for the rf analog section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 1 has a value 3 v 10%. v dd 1 must have the same voltage as v dd 2, v dd 3, and dv dd . v p 1 rf charge pump power supply. decoupling capacitors to the ground plane should be placed as close as possible to this pin. this voltage should be greater than or equal to v dd 1.
rev. b ? ADF4252 ADF4252 2 doubler output mux v dd d gnd v dd n div r div high z 4-bit r counter phase frequency detector lock detect charge pump reference ref in ref out v dd 1 v dd 2 v dd 3 dv dd v p 1 v p 2 r set 24-bit data register clk data le fraction reg modulus reg integer reg n counter third order fractional interpolator rf in a rf in b cp rf 6-bit if a counter cp if 2 doubler 15-bit r counter charge pump phase frequency detector 12-bit if b counter if pre- scaler muxout a gnd 1 a gnd 2 d gnd cp gnd 1 cp gnd 2 if in b if in a figure 2. detailed functional block diagram
rev. b t ypical performance characteristics?df4252 ? tpc plots 1 to 12 attained using eval-ADF4252eb1; measurements from hp8562e spectrum analyzer. frequency 0 ?0 ?khz ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 99.19dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm output power (db) tpc 1. phase noise plot, lowest noise mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?khz ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?0.36dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm output power (db) tpc 2. phase noise plot, low noise and spur mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?khz ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?5.86dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm output power (db) tpc 3. phase noise plot, lowest spur mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?0dbc@ 100khz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?00khz ?00khz 1.7518ghz 200khz 400khz output power (db) tpc 4. spurious plot, lowest noise mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?00khz ?00khz 1.7518ghz 200khz 400khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?1dbc@ 100khz output power (db) tpc 5. spurious plot, low noise and spur mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?00khz ?00khz 1.7518ghz 200khz 400khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 10mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?2dbc@ 100khz output power (db) tpc 6. spurious plot, lowest spur mode, 1.7518 ghz rf out , 10 mhz pfd frequency, 200 khz channel step resolution
rev. b ? ADF4252 frequency 0 ?0 ?khz ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?02dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm output power (db) tpc 7. phase noise plot, lowest noise mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?khz ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?3.86dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm output power (db) tpc 8. phase noise plot, low noise and spur mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?khz output power (db) ?khz 1.7518ghz 1khz 2khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?9.52dbc/hz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 10hz reference level = 4.2dbm tpc 9. phase noise plot, lowest spur mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 output power (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?3dbc@ 100khz v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?00khz ?00khz 1.7518ghz 200khz 400khz tpc 10. spurious plot, lowest noise mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?00khz output power (db) ?00khz 1.7518ghz 200khz 400khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?3.2dbc@ 100khz tpc 11. spurious plot, low noise and spur mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution frequency 0 ?0 ?00khz output power (db) ?00khz 1.7518ghz 200khz 400khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 v dd = 3v, v p = 5v i cp = 1.875ma pfd frequency = 20mhz channel step = 200khz loop bandwidth = 20khz fraction = 59/100 rbw = 1khz reference level = 4.2dbm ?2.33dbc@ 100khz tpc 12. spurious plot, lowest spur mode, 1.7518 ghz rf out , 20 mhz pfd frequency, 200 khz channel step resolution
rev. b ADF4252 ? * across all fractional channel steps from f = 0/130 to f = 129/130. rf out = 1.45 ghz, int reg = 55, ref = 26 mhz, and lbw = 40 khz. plots attained using eval-ADF4252eb2 evaluation board. frequency (ghz) ?0 ?20 1.430 1.460 1.435 phase noise (dbc/hz) 1.440 1.445 1.450 1.455 ?5 ?0 ?05 ?10 ?15 ?0 ?5 ?5 ?00 lowest spur mode low noise and spur mode lowest noise mode tpc 13. in-band phase noise vs. frequency* frequency (ghz) ?0 ?10 1.430 1.460 1.435 spurious level (dbc) 1.440 1.445 1.450 1.455 ?0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 lowest noise mode lowest spur mode tpc 14. 100 khz spur vs. frequency* frequency (ghz) ?0 ?20 1.430 1.460 1.435 spurious level (dbc) 1.440 1.445 1.450 1.455 ?0 ?0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 lowest noise mode lowest spur mode tpc 15. 200 khz spur vs. frequency* frequency (ghz) ?0 ?20 1.430 1.460 1.435 spurious level (dbc) 1.440 1.445 1.450 1.455 ?0 ?0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 lowest noise mode lowest spur mode tpc 16. 400 khz spur vs. frequency* frequency (ghz) ?0 ?20 1.430 1.460 1.435 spurious level (dbc) 1.440 1.445 1.450 1.455 ?0 ?0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 lowest noise mode lowest spur mode tpc 17. 600 khz spur vs. frequency* frequency (ghz) ?0 ?20 1.430 1.460 1.435 spurious level (dbc) 1.440 1.445 1.450 1.455 ?0 ?0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 lowest noise mode lowest spur mode tpc 18. 3 mhz spur vs. frequency*
rev. b ?0 ADF4252 frequency (ghz) 0 ?5 06 1 amplitude (dbm) 2345 ? ?0 ?5 ?5 ?0 ?0 prescaler = 4/5 prescaler = 8/9 tpc 19. rf input sensitivity if input frequency (ghz) 0 5 35 ?.4 1.6 0.1 if input power (dbm) 0.6 1.1 15 20 25 30 10 40 v dd = 3v v p 2 = 3v tpc 20. if input sensitivity phase detector frequency (hz) ?20 ?30 ?80 10k 10m 100k phase noise (db/hz) 1m ?50 ?60 ?70 ?40 v dd = 3v v p = 5v tpc 21. phase noise (referred to cp output) vs. pfd frequency, rf side phase detector frequency (hz) ?20 ?30 ?80 10k 10m 100k phase noise (db/hz) 1m ?50 ?60 ?70 ?40 v dd = 3v v p = 3v tpc 22. phase noise (referred to cp output) vs. pfd frequency, if side v cp (v) 6 4 0 0.5 i cp (ma) 1.5 0 ? ? 2 ? v dd = 3v v p 1 = 5.5v 1.0 2.0 3.0 2.5 4.0 3.5 4.5 5.5 5.0 tpc 23. rf charge pump output characteristics v cp (v) 6 4 0 0.5 i cp (ma) 1.5 0 ? ? 2 ? v dd = 3v v p 2 = 3v 1.0 2.0 3.0 2.5 tpc 24. if charge pump output characteristics
rev. b ADF4252 ?1 circuit description reference input section the reference input stage is shown in figure 3. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. power-down control ref in nc nc no sw3 sw2 sw1 100k bu ffer to r counter nc = normally closed no = normally open ref out xoeb figure 3. reference input stage rf and if input stage the rf input stage is shown in figure 4. the if input stage is the same. it is followed by a two-stage limiting amplifier to generate the cml clock levels needed for the n counter. 2k 2k 1.6v bias generator rf in a rf in b v dd 1 a gnd figure 4. rf input stage rf int divider the rf int cmos counter allows a division ratio in the pll feedback counter. division ratios from 31 to 255 are allowed. int, frac, mod, and r relationship the int, frac, and mod values, in conjunction with the rf r counter, make it possible to generate output frequencies that are spaced by fractions of the rf phase frequency detector (pfd). the equation for the rf vco frequency ( rf out ) is rf f int frac mod out pfd = + ? ? ? ? ? ? (1) where rf out is the output frequency of external voltage controlled oscillator (vco). fref d r pfd in = + () 1 (2) ref in = the reference input frequency, d = rf ref in doubler b it, r = the pr eset divide ratio of the binary 4-bit program- mable reference counter (1 to 15), int = the preset divide ratio of the binary 8-bit counter (31 to 255), mod = the preset modulus ratio of binary 12-bit programmable frac counter (2 to 4095), and frac = the preset fractional ratio of the binary 12-bit programmable frac counter (0 to mod). n = int + frac/mod f rom rf input stage to pfd rf n divider third order f ractional in terpolator mod reg int reg frac value n-counter figure 5. n counter rf r counter the 4-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the rf pfd. division ratios from 1 to 15 are allowed. if r counter the 15-bit if r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the if pfd. division ratios from 1 to 32767 are allowed. if prescaler (p/p + 1) the dual modulus if prescaler (p/p + 1), along with the if a and b counters, enables the large division ratio, n, to be realized (n = pb + a). operating at cml levels, it takes the clock from the if input stage and divides it down to a manageable frequency for the cmos if a and b counters. if a and b counters the if a and b cmos counters combine with the dual modulus if prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are guaranteed to work when the prescaler output is 150 mhz or less. pulse swallow function the if a and b counters, in conjunction with the dual modulus if prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. see device programming after initial power-up section for examples. the equation for the if vco ( if out ) frequency is if p b a f out pfd = () + [] (3) where if out = the output frequency of the external voltage controlled oscillator (vco), p = the preset modulus of if dual modulus prescaler, b = the preset divide ratio of the binary 12-bit counter (3 to 4095), and a = the preset divide ratio of the binary 6-bit swallow counter (0 to 63). f pfd is obtained using equation 2.
rev. b ?2 ADF4252 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 6 is a simplified schematic. the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. +in d1 q1 clr1 u1 u3 delay element hi up d2 q2 clr2 u2 hi down charge pump cp ?n figure 6. pfd simplified schematic muxout and lock detect the output multiplexer on the ADF4252 allows the user to access various internal points on the chip. the state of muxout is controlled by m4, m3, m2, and m1 in the master register. table i shows the full truth table. figure 7 shows the muxout section in block diagram format. logic low if analog lock detect if r divider output if n divider output rf analog lock detect if/rf analog lock detect if digital lock detect logic high rf r divider output rf n divider output three state output rf digital lock detect rf/if digital lock detect logic high logic low mux control muxout dv dd d gnd figure 7. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital and analog. digital is active high. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k ? nominal. when lock has been detected, this output will be high with narrow low going pulses. input shift register data is clocked in on each rising edge of clk. the data is clocked in msb first. data is transferred from the input register to one of seven latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c2, c1, and c0) in the shift register. these are the three lsbs: db2, db1, and db0, as shown in figure 1. the truth table for these bits is shown in table i. table ii summarizes how the registers are programmed. table i. control bit truth table c2 c1 c0 data latch 000 rf n divider reg 001 rf r divider reg 010 rf control reg 011 master reg 100 if n divider reg 101 if r divider reg 110 if control reg
rev. b ADF4252 ?3 table ii. register summary rf control reg db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 p13 a6 6-bit if a counter 12-bit if b counter db21 if prescaler db22 db23 if cp gain p14 p15 c3 (1) db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r15 p16 15-bit if r counter c3 (1) r14 if ref in d oubler rf n divider reg if r divider reg rf r divider reg db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 p2 p3 12-bit interpolator modulus value (mod) c3 (0) 4-bit rf r counter r2 pres caler rf ref in d oubler ma ster reg if n divider reg if control reg db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) p9 p10 p11 p12 m1 m2 m3 m4 mux out c3 (0) xo dis able p ower- d own cp three- stat e c ounter r eset db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 c ontrol bits 12-bit rf fractional value (frac) db23 db22 db21 n7 r eserved n8 p1 c3 (0) 8-bit rf integer value (int) n2 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) p4 p5 p6 n1 p8 0 cp1 cp2 n2 t1 t2 t3 n3 rf cp c urrent s etting rf pd po larity c3 (0) r eserved n oise and spur s etting 1 rf p ower- d own rf cp three- stat e rf c ounter r eset r eserved n oise and spur s etting 2 n oise and spur s etting 3 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) p17 p18 p19 p20 p21 cp1 cp2 cp3 pr1 t7 t8 pr2 pr3 if cp current if pd po larity c3 (1) r eserved if ldp if power- d own if cp three- stat e if c ounter r eset rf phase r esync rf phase r esync s etting c ontrol bits c ontrol bits c ontrol bits c ontrol bits c ontrol bits c ontrol bits
rev. b ?4 ADF4252 table iii. rf n divider register map f12 f11 f10 f3 f2 f1 fractional value (frac) 000 .......... 0 0 0 0 000 .......... 0 0 1 1 000 .......... 0 1 0 2 000 .......... 0 1 1 3 ... .......... . . . . ... .......... . . . . ... .......... . . . . 111 .......... 1 0 0 4092 111 .......... 1 0 1 4093 111 .......... 1 1 0 4094 111 .......... 1 1 1 4095 rf integer n8 n7 n6 n5 n4 n3 n2 n1 00011111 31 00100000 32 00100001 33 00100010 34 ........ . ........ . ........ . 11111101 253 11111110 254 11111111 255 p1 0 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 c ontrol bits 12-bit rf fractional value (frac) db23 db22 db21 n7 n8 p1 c3 (0) 8-bit rf integer value (int) n2 reserved va lue (int) * * when p = 8/9, n min = 91 r eserved r eserved
rev. b ADF4252 ?5 table iv. rf r divider register map interp olator modulus m12 m11 m10 m3 m2 m1 value (mod) divide ratio 000 .......... 0102 000 .......... 0113 000 .......... 1004 ... .......... .... ... .......... .... ... .......... .... 111 .......... 100 4092 111 .......... 101 4093 111 .......... 110 4094 111 .......... 111 4095 rf r counter r4 r3 r2 r1 divide ratio 00011 00102 00113 ..... ..... ..... 110113 111014 111115 p2 rf ref in d oubler 0dis abled 1e nabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 p2 p3 c ontrol bits 12-bit interpolator modulus value (mod) c3 (0) 4-bit rf r counter r2 rf ref in d oubler p re- scaler p3 rf prescaler 0 4/5 1 8/9
rev. b ?6 ADF4252 table v. rf control register map p6 rf power-down 0dis abled 1en abled db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) p4 p5 p6 n1 p8 0 cp1 cp2 n2 t1 t2 t3 n3 c ontrol bits rf cp c urrent s etting rf pd po larity c3 (0) r eserved n oise and spur s etting 1 rf power- d own rf cp three- stat e rf c ounter r eset r eserved n oise and spur s etting 2 n oise and spur s etting 3 i cp (ma) cp2 cp1 1.5k 2.7k 5.6k 00 1.125 0.625 0.301 01 3.375 1.875 0.904 10 5.625 3.125 1.506 11 7.7875 4.375 2.109 p8 rf pd polarity 0ne gative 1posit ive p5 rf cp three-state 0dis abled 1t hree-state p4 rf counter r eset 0dis abled 1enab led n3 n2 n1 noise and spur setting 000lowest spur 001low noise and spur 111lowest noise th ese bits should each be set to 0 for n ormal operation
rev. b ADF4252 ?7 table vi. master register map p11 0 1 p12 0 xo enabled (ref out = ref in ) 1 xo disabled (ref out = logic low) (ref out = logic high when in power-down) p10 0 1 p9 0 1 0 0 0 0 logic low 0 0 0 1 if analog lock detect 0 0 1 0 if r divider output 0 0 1 1 if n divider output 0 1 0 0 rf analog lock detect 0 1 0 1 rf/if analog lock detect 0 1 1 0 if digital lock detect 0 1 1 1 logic high 1 0 0 0 rf r divider output 1 0 0 1 rf n divider output 1 0 1 0 three-state output 1 0 1 1 logic low 1 1 0 0 rf digital lock detect 1 1 0 1 rf/if digital lock detect 1 1 1 0 logic high 1 1 1 1 logic low db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) p9 p10 p11 p12 m1 m2 m3 m4 c ontrol bits mux out c3 (0) xo dis able p ower- d own cp three- stat e c ounter r eset mux out m1 m2 m3 m4 c ounter reset dis abled e nabled cp three-state dis abled three-state p ower-down dis abled e nabled xo disable
rev. b ?8 ADF4252 table vii. if n divider register map b12 b11 b10 b3 b2 b1 b counter divide ratio 000 .......... 0113 000 .......... 1004 ... .......... .... ... .......... .... ... .......... .... 111 .......... 100 4092 111 .......... 101 4093 111 .......... 110 4094 111 .......... 111 4095 a counter a6 a5 .......... a2 a1 divide ratio 00 .......... 0 0 0 00 .......... 0 1 1 00 .......... 1 0 2 00 .......... 1 1 3 .. .......... . . . .. .......... . . . .. .......... . . . 11 .......... 0 0 60 11 .......... 0 1 61 11 .......... 1 0 62 11 .......... 1 1 63 * n = bp + a, p is prescaler value. b must be greater than or equal to a for contiguous values of n, n min is (p 2 p) . p14 p13 prescaler value 00 8/9 01 16/17 10 32/33 11 64/65 p15 if cp gain 0dis abled 1e nabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 p13 a6 c ontrol bits 6-bit if a counter * 12-bit if b counter * db21 if pres caler * db22 db23 if cp g ain p14 p15 c3 (1)
rev. b ADF4252 ?9 table viii. if r divider register map r14 r13 r12 .......... r3 r2 r1 divide ratio 000 .......... 0011 000 .......... 0102 000 .......... 0113 000 .......... 1004 ... .......... .... ... .......... .... ... .......... .... 111 .......... 100 16380 111 .......... 101 16381 111 .......... 110 16382 111 .......... 111 16383 p16 if ref in d oubler 0dis abled 1e nabled db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r15 p16 c ontrol bits 15-bit if r counter c3 (1) r14 if ref in d oubler r15 0 0 0 0 . . . 32764 32765 32766 32767
rev. b ?0 ADF4252 table ix. if control register map p19 if power-down 0dis abled 1e nabled p20 if ldp 03 15 if cp3 if cp2 if cp1 1.5k 2.7k 5.6k 00 0 1.125 0.625 0.301 00 1 2.25 1.25 0.602 01 0 3.375 1.875 0.904 01 1 4.5 2.5 1.205 10 0 5.625 3.125 1.506 10 1 6.75 3.75 1.808 11 0 7.7875 4.375 2.109 11 19 5.0 2.411 p21 if pd polarity 0ne gative 1pos itive p18 if cp three-state 0dis abled 1t hree-state p17 if counter reset 0dis abled 1e nabled db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) p17 p18 p19 p20 p21 cp1 cp2 cp3 pr1 t7 t8 pr2 pr3 c ontrol bits if cp current s etting if pd po larity c3 (1) r eserved if ldp if power- d own if cp three- stat e if c ounter r eset rf phase r esync rf phase r esync th ese bits should be set to 0 for normal operation pr3 pr2 pr1 rf phase resync 000disabled 111e nabled i cp (ma)
rev. b ADF4252 e21e rf n divider register (address r0) with r0[2, 1, 0] set to [0, 0, 0], the on-chip rf n divider register will be programmed. table iii shows the input data format for programming this register. 8-bit rf int value these eight bits control what is loaded as the int value. this is used to determine the overall feedback division factor. it is used in equation 1. 12-bit rf frac value these 12 bits control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is used in equation 1. the frac value must be less than or equal to the value loaded into the mod register. rf r divider register (address r1) with r1[2, 1, 0] set to [0, 0, 1], the on-chip rf r divider register will be programmed. table iv shows the input data format for programming this register. rf prescaler (p/p + 1) the rf dual-modulus prescaler (p/p +1), along with the int, frac, and mod counters, determine the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down to am anageable frequency for the cmos counters. it is based on a synchron ous 4/5 core (see table iv). rf ref in doubler setting this bit to 0 feeds the ref in signal directly to the 4-bit rf r counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 4-bit rf r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional-n synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and lowest spur mode is chosen, the in-band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to ref in duty cycle in the lowest noise mode and in low noise and spur mode. the phase noise is insensitive to ref in duty cycle when the doubler is disabled. 4-bit rf r counter the 4-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 15 are allowed. 12-bit interpolator modulus this programmable register sets the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. rf control register (address r2) with r2[2, 1, 0] set to [0, 1, 0], the on-chip rf control register will be programmed. table v shows the input data format for programming this register. upon initialization, db15 ? db11 should all be set to 0. noise and spur setting the noise and spur setting (r2[15, 11, 06]) is a feature that allows the user to optimize his or her design either for improved spurious performance or for improved phase noise performance. when set to [0, 0, 0], the lowest spurs setting is chosen. here, dither is enabled. this randomizes the fractional quantization noise so that it looks more like white noise than spurious noise. this means that the part is optimized for improved spurious performance. this operation would normally be used when the pll closed-loop bandwidth is wide 1 , for fastlocking applications. a wide-loop filter does not attenuate the spurs to a level that a narrow-loop 2 bandwidth would. when this bit is set to [0, 0, 1], the low noise and spur setting is enabled. here, dither is disabled. this optimizes the synthesizer to operate with improved noise performance. however, the spurious performance is degraded in this mode compared to lowest spurs setting. to improve noise performance even further, another option is available that reduces the phase noise. this is the lowest noise setting [1, 1, 1]. as well as disabling the dither, it also ensures the charge pump is oper- ating in an optimum region for noise performance. this setting is extremely useful where a narrow-loop filter bandwidth is available. the synthesizer ensures extremely low noise and the filter attenu- ates the spurs. the typical performance characteristics (tpcs) give the user an idea of the trade-off in a typical wcdma setup for the different noise and spur settings. rf counter reset db3 is the rf counter reset bit for the ADF4252. when this is 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be 0. rf charge pump three-state this bit puts the charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. rf power-down db5 on the ADF4252 provides the programmable power-down mode. setting this bit to a 1 will perform a power-down on both the rf and if sections. setting this bit to 0 will return the rf and if sections to normal operation. while in software p ower-down, the part will retain all information in its registers. only when supplies are removed will the register contents be lost. when a power-down is activated, the following events occur: 1. all active rf dc current paths are removed. 2. the rf synthesizer counters are forced to their load state conditions. 3. the rf charge pump is forced into three-state mode. 4. the rf digital lock detect circuitry is reset. 5. the rf in input is debiased. 6. the input register remains active and capable of loading and latching data. notes 1 wide-loop bandwidth is seen as a loop bandwidth greater than 1/10th of the rf out channel step resolution (f res ). 2 narrow-loop bandwidth is seen as a loop bandwidth less than 1/10th of the rf out channel step resolution (f res ).
rev. b e22e ADF4252 rf phase detector polarity db7 in the ADF4252 sets the rf phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. rf charge pump current setting db9 and db10 set the rf charge pump current setting. this should be set to whatever charge pump current the loop filter has been designed with (see table v). rf test modes these bits should be set to 0, 0, 0 for normal operation. master register (address r3) with r3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be programmed. table vi shows the input data format for program- ming the master register. rf and if counter reset db3 is the counter reset bit for the ADF4252. when this is 1, both the rf and if r, int, and mod counters are held in reset. for normal operation, this bit should be 0. upon power-up, the db3 bit needs to be disabled, the int counter resumes counting in ? close ? alignment with the r counter. (the maximum error is one prescaler cycle). charge pump three-state this bit puts both the rf and if charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. power-down r3[3] on the ADF4252 provides the programmable power-down mode. setting this bit to a 1 will perform a power-down on both the rf and if sections. setting this bit to 0 will return the rf and if sections to normal operation. while in software power- down, the part will retain all information in its registers. only when supplies are removed will the register contents be lost. when a power-down is activated, the following events occur: 1. all active dc current paths are removed. 2. the rf and if counters are forced to their load state conditions. 3. the rf and if charge pumps are forced into three-state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input and if in input are debiased. 6. the oscillator input buffer circuitry is disabled. 7. the input register remains active and capable of loading and latching data. xo disable setting this bit to 1 disables the ref out circuitry. this will be set to 1 when using an external tcxo, vcxo, or other reference sources. this will be set to 0 when using the ref in and ref out pins to form an oscillator circuit. muxout control the on-chip multiplexer is controlled by r3[10 ? 7] on the ADF4252. table vi shows the truth table. if the user updates the rf control register or the if control register, the muxout contents will be lost. to retrieve the muxout signal, the user must write to the master register. lock detect the digital lock detect output goes high if there are 40 successive pfd cycles with an input error of less than 15 ns. it stays high until a new channel is programmed or until the error at the pfd input exceeds 30 ns for one or more cycles. if the loop bandwidth is narrow compared to the pfd frequency, the error at the pfd inputs may drop below 15 ns for 40 cycles around a cycle slip; thus the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. in this case the digital lock detect is reliable only as a ? loss of lock ? indicator. if n divider register (address r4) with r4[2, 1, 0] set to [1, 0, 0], the on-chip if n divider register will be programmed. table vii shows the input data format for programming this register. if cp gain when set to 1, this bit changes the if charge pump current setting to its maximum value. when the bit is set to 0, the charge pump current reverts back to its previous state. if prescaler the dual-modulus prescaler (p/p + 1), along with the if a and b counters, determine the overall division ratio, n, to be realized (n = pb + a) from the if in to the if pfd input. operating at cml levels, it takes the clock from the if input stage and divides it d own to a manageable frequency for the cmos counters. it is based on a synchronous 4/5 core. see equation 2 and table vii. if b and a counter the if a and b counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency (ref in ) divided by r. the equation for the if out vco frequency is given in equation 2. if r divider register (address r5) with r5[2, 1, 0] set to [1, 0, 1], the on-chip if r divider register will be programmed. table viii shows the input data format for programming this register. if ref in doubler setting this bit to 0 feeds the ref in signal directly to the 15-bit if r counter. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 15-bit if r counter. 15-bit if r counter the 15-bit if r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the if phase frequency detector (pfd). division ratios from 1 to 32767 are allowed. if control register (address r6) with r6[2, 1, 0] set to [1, 1, 0], the on-chip if control register will be programmed. table ix shows the input data format for programming this register. upon initialization, db15 ? db11 should all be set to 0.
rev. b ADF4252 ?3 if counter reset db3 is the if counter reset bit for the ADF4252. when this is 1, the if synthesizer counters are held in reset. for normal operation, this bit should be 0. if charge pump three-state this bit puts the if charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. if power-down db5 on the ADF4252 provides the programmable power-down mode. setting this bit to a 1 will perform a power-down on the if section. setting this bit to 0 will return the section to normal operation. while in software power-down, the part will retain all information in its registers. only when supplies are removed will the register contents be lost. when a power-down is activated, the following events occur: 1. all active if dc current paths are removed. 2. the if synthesizer counters are forced to their load state conditions. 3. the if charge pump is forced into three-state mode. 4. the if digital lock detect circuitry is reset. 5. the if in input is debiased. 6. the input register remains active and capable of loading and latching data. if phase detector polarity db7 in the ADF4252 sets the if phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. if charge pump current setting db8, db9, and db10 set the if charge pump current setting. this should be set to whatever charge pump current the loop filter has been designed with (see table vii). if test modes these bits should be set to [0, 0] for normal operation. rf phase resync setting the phase resync bits [15, 14, 11] to [1, 1, 1] enables the phase resync feature. with a fractional modulus of m, a fractional-n pll can settle with any one of (2 )/m valid phase offsets with respect to the reference input. this is different to integer-n (where the rf output always settles to the same static phase offset with respect to the input reference, which is zero ideally) but does not matter in most applications where all that is required is consistent frequency lock. for applications where a consistent phase relationship between the output and reference is required (i.e., digital beamforming), the ADF4252 fractional-n synthesizer can be used with the phase resync feature enabled. this ensures that if the user pro grams the pll to jump from frequency (and phase) a to f requency (and phase) b and back again to frequency a, the pll will return to the original phase (phase a). when enabled, it will activate every time the user programs register r0 or r1 to set a new output frequency. however if a cycle slip occurs in the settling transient after the phase re-resync operation, the phase resync will be lost. this can be avoided by delaying the resync activation until the locking transient is close to its final frequency. in the if r divider register, bits r5[17 C 3] are used to set a time interval from when the new channel is pro- grammed to the time the resync is activated. although the time interval resolution available from the 15-bit if r register is one ref in clock cycle, if r should be programmed to be a value that is an integer multiple of the programmed mod value to set a time interval that is at least as long as the rf pll loop s lock time. for example, if ref in = 26 mhz, mod = 130 to give 200 khz output steps (f res ), and the rf loop has a settling time of 150 s, then if_r should be programmed to 3900, as 26 150 3900 mhz s = note that if it is required to use the if synthesizer with phase resync enabled on the rf synth, the if synth must operate with a pfd frequency of 26 mhz/3900. in an application where the if synth is not required, the user should ensure that registers r4 and r6 are not programmed so that the rest of the if circuitry remains in power-down. device programming after initial power-up after initially applying power to the supply pins, there are three ways to operate the device. rf and if synthesizers operational all registers must be written to when powering up both the rf and if synthesizer. rf synthesizer operational, if power-down it is necessary to write only to registers r3, r2, r1, and r0 when powering up the rf synthesizer only. the if side will remain in power-down until registers r6, r5, r4, and r3 are written to. if synthesizer operational, rf power-down it is necessary to write to only registers r6, r5, r4, and r3 when powering up the if synthesizer only. the rf side will remain in power-down until registers r3, r2, r1, and r0 are written to. rf synthesizer: an example t he rf synthesizer should be programmed as follows: rf int frac mod f out pfd =+ ? ? ? ? ? ? (4) where rf out = the rf frequency output, int = the integer division f actor, frac = the fractionality, and mod = the modulus. f ref d r pfd in = + ? ? ? ? ? ? 1 (5) where ref in = the reference frequency input, d = the rf ref in doubler bit, and r = the rf reference division factor. for example, in a gsm 1800 system where 1.8 ghz rf frequency output (rf out ) is required, a 13 mhz reference frequency input ( ref in ) is available and a 200 khz channel resolution ( f res ) is required on the rf output. mod ref f mod in res = == 13 200 65 mhz khz
rev. b ?4 ADF4252 so, from equation 5: fmhz pfd = + = = ? ? ? ? ? ? 13 10 1 13 18 13 mhz . ghz mhz int + frac 65 where int = 138 and frac = 30. if synthesizer: an example the if synthesizer should be programmed as follows: if p b a f out pfd = () + [] (6) where if out = the output frequency of external voltage controlled oscillator (vco), p = the if prescaler, b = the b counter value, and a = the a counter value. equation 5 applies in this example as well. for example, in a gsm1800 system, where 540 mhz if fre- quency output (if out ) is required, a 13 mhz reference frequency i nput (ref in ) is available and a 200 khz channel resolution (f res ) is required on the if output. the prescaler is set to 16/17. if ref in doubler is disabled. by equation 5, 200 13 10 khz mhz = + r if r = 65. by equation 6, 540 200 16 mhz khz = () + [] ba if b = 168 and a = 12. modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in would set the modulus to 65. this means that the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. reference doubler and reference divider there is a reference doubler on-chip, which allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency will usually result in an improvement in noise performance of 3 db. it is important to note that the pfd can- not be operated above 30 mhz due to a limitation in the speed of the - circuit of the n divider. 12-bit programmable modulus unlike most other fractional-n plls, the ADF4252 allows the user to program the modulus over a 12-bit range. this means that the user can set up the part in many different configurations for a specific application, when combined with the reference doubler and the 4-bit r counter. for example, in an application that requires 1.75 ghz rf and 200 khz channel step resolution, the system has a 13 mhz reference signal. one possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this results in the required 200 khz resolution. another possible setup is using the reference doubler to create 26 mhz from the 13 mhz input signal. this 26 mhz is then fed into the pfd. the modulus is now programmed to divide by 130, which also results in 200 khz resolution. this offers supe- rior phase noise performance over the previous setup. the programmable modulus is also very useful for multistandard applications. if a dual-mode phone requires pdc and gsm1800 standards, the programmable modulus is a huge benefit. pdc requires 25 khz channel step resolution, whereas gsm1800 requires 200 khz channel step resolution. a 13 mhz reference signal could be fed directly to the pfd. the modulus would then be programmed to 520 when in pdc mode (13 mhz /520 = 25 khz). the modulus would be reprogrammed to 65 for gsm1800 op eration (13 mhz/65 = 200 khz). it is important that the pfd frequency remains constant (13 mhz). this allows the user to design one loop filter that can be used in both setups without any stability issues. it is the ratio of the rf frequency to the pfd frequency that affects the loop design. keeping this relationship constant, and instead changing the modulus factor, results in a stable filter. spurious optimization and fastlock as mentioned in the noise and spur setting section, the part can be optimized for spurious performance. however, in fastlocking applications, the loop bandwidth needs to be wide. therefore, the filter does not provide much attenuation of the spurious. the programmable charge pump can be used to avoid this issue. the filter is designed for a narrow- loop bandwidth so that steady- state spurious specifications are met. this is designed using the low- est charge pump current setting. to implement fastlock during a frequency jump, the charge pump current is set to the maxi- mum setting for the duration of the jump. this has the effect of widening the loop bandwidth, which improves lock time. when the pll has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. this will narrow the loop bandwidth to its original cutoff frequency to allow for better attenuation of the spurious than the wide-loop bandwidth. spurious signals predicting where they will appear just as in integer-n plls, spurs will appear at pfd frequency offsets on either side of the carrier (and multiples of the pfd frequency). in a fractional-n pll, spurs will also appear at frequencies equal to the rf out channel step resolution (f res ). the ADF4252 uses a high order fractional interpolator engine, which results in spurs also appearing at frequencies equal to half of the channel step resolution. for example, examine the gsm1800 setup with a 26 mhz pfd and 200 khz resolution. spurs w ill appear at 26 mhz from the rf carrier (at an extremely low level due to filtering). also, there will be spurs at 200 khz from the rf carrier. due to the fractional interpolator architecture used in the ADF4252, spurs will also appear at
rev. b ADF4252 ?5 100 khz from the rf carrier. harmonics of all spurs mentioned will also appear. w ith the lowest spur setting enabled, the spurs will be attenuated into the noise floor. prescaler the prescaler limits the int value. with p = 4/5, nmin = 31. with p = 8/9, nmin = 91. the prescaler can also influence the phase noise performance. if int < 91, a prescaler of 4/5 should be used. for applications where int > 91, p = 8/9 should be used for optimum noise performance. filter design adisimpll a filter design and analysis program is available to help users implement their pll design. visit www.analog.com/pll for a free download of the adisimpll software. the software designs, simulates, and analyzes the entire pll frequency domain and time domain response. various passive and active filter architectures are allowed. interfacing the ADF4252 has a simple spi compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of sclk will be transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the control bit truth table. the maximum allowable serial clock rate is 20 mhz , which means that the maximum update rate possible for the device is 833 khz or one update every 1.2 s. this is certainly more than adequate for systems that will have typical lock times in hun- dreds of microseconds. aduc812 ADF4252 sclk sdata le ce muxout (lock detect) sclock mosi i/o ports figure 8. aduc812 to ADF4252 interface aduc812 interface figure 8 shows the interface between the ADF4252 and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF4252 needs (at most) a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed will be 166 khz. adsp-21xx ADF4252 sclk sdata le ce muxout (lock detect) sclk dt i/o flags tfs figure 9. adsp-21xx to ADF4252 interface adsp-2181 interface figure 9 shows the interface between the ADF4252 and the adsp-21xx digital signal processor. each latch of the ADF4252 needs (at most) a 24-bit word. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit m ode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. pcb design guidelines for chip scale package the leads on the chip scale package (cp-24) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this will ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this will ensure that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. the user should connect the printed circuit board to a gnd .
rev. b ?6 ADF4252 if out j6 c15 100pf r12 18 r13 18 c16 100pf vco2 rf out vcc v in 10 14 2 c4 10pf c3 22 f 6.3v r48 0 vvco r17 13k c20 82pf c19 2.2nf c18 270pf r16 7.5k r15 51 c17 100pf r14 18 c10 10pf c9 22 f 6.3v r44 0 v p c6 10pf c5 22 f 6.3v c8 10pf c7 22 f 6.3v v dd 1 v dd 2 v dd 3 dv dd v p 2 cp if if in a r43 0 r1 20 vdd v dd rf out j7 c27 100pf r22 18 r21 18 c26 100pf vco1 rf out vcc v in 10 14 2 c30 10pf c29 22 f 6.3v r49 0 vvco r20 470 c25 3.3nf c24 100nf c23 10nf r19 270 r24 51 c28 100pf r23 18 c12 10pf c11 22 f 6.3v v p v p 1 cp rf rf in a c44 100pf cp gnd 1 rf in b a gnd 1 d gnd a gnd 2 cp gnd 2 muxout r27 10k t16 r28 10k r29 10k d4 v dd clk c43 100pf r27 2.7k data le t14 r39 0 r26 1k r4 1m r11 51 y2 10mhz c31 33pf c32 33pf c14 1nf c13 1nf ref in j5 t13 r47 0 y3 b+ o/p 4 3 2 gnd c45 10pf c46 22 f r46 0 r45 0 3v 5v u1 ADF4252bcp ref out j8 r38 0 u6 1 2 4 vcc r35 0 r34 0 5v 3v vco190?40t vco190?730t figure 10. typical pll circuit schematic
rev. b ADF4252 ?7 outline dimensions 24-lead lead frame chip scale package [lfcsp] (cp-24) dimensions shown in millimeters 1 24 6 7 13 19 18 bottom view 12 2.25 2.10 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1 .00 0 .85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.0 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 sq 0.20 ref 0.25 min compliant to jedec standards mo-220-vggd-2
rev. b c02946??0/03(b) ?8 ADF4252 revision history location page 10/03?ata sheet changed from rev. a to rev. b. change to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 change to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 change to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 inserted lock detect section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 change to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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